1. Field of the Invention
The present invention relates to a layout structure of a reflective LCD (liquid crystal display), and particularly, to a reflective LCD configured to change a gate-line scanning direction depending on usage (for example, overhead usage and desktop usage) of the LCD and reduce the influence of the feed-through characteristics of a pixel A caused depending on a gate-line scanning direction when the pixel A is arranged adjacent to a pixel B in the same column.
2. Description of Related Art
Recently, projection LCDs to display images on large screens are extensively used for, for example, outdoor public displays, control operation displays, and high-resolution image displays conforming to hi-vision broadcast standards and SVGA computer graphics standards.
The projection LCDs are largely classified into transmission LCDs based on a transmission method and reflective LCDs based on a reflection method. The transmission LCDs have a drawback that a TFT (thin film transistor) formed in each pixel is unable to serve as a transmission area to transmit light, and therefore, reduces a numerical aperture. For this reason, the reflective LCDs are attracting attention.
Generally, the reflective LCD employs a semiconductor substrate (Si substrate) on which a plurality of switching elements and storage capacitors for the switching elements are formed and are electrically isolated pixel by pixel. Over the switching elements and storage capacitors, a plurality of functional films are formed one upon another. The top one of the functional films is a metal film that forms a plurality of reflective pixel electrodes that are electrically isolated from one another. One switching element, one storage capacitor connected to the switching element, and one reflective pixel electrode connected to the switching element form a pixel. Such pixels are arranged in rows and columns to form a matrix on the semiconductor substrate. Facing the reflective pixel electrodes, a transparent counter electrode commonly serving for all pixels is formed on the reverse of a transparent substrate. Between the reflective pixel electrodes and the counter electrode, liquid crystals are sealed to form the reflective LCD. From the transparent substrate side, color-image read light is made incident through the counter electrode to the liquid crystals. At this time, the switching elements are driven to change potential differences between the reflective pixel electrodes and the counter electrode in response to video signals, to control orientation of the liquid crystals, modulate and reflect the color-image read light by the reflective pixel electrodes, and emit the light from the transparent substrate.
FIG. 1 is an enlarged view showing a model of a pixel in a reflective LCD according to a related art 1. FIG. 1 corresponds to a sectional view taken along an arrow line X-Y of FIG. 5. FIGS. 2A and 2B are explanatory views showing an active-matrix drive circuit in the reflective LCD of the related art 1, in which FIG. 2A is a block diagram showing the active-matrix drive circuit and FIG. 2B is an enlarged circuit diagram showing a transistor area shown in FIG. 2A.
The reflective LCD 10A of the related art 1 of FIG. 1 is designed for a standard reflective projector. Among a plurality of pixels of the LCD 10A to display images, one pixel will be enlarged and explained. A semiconductor substrate 11 serving as a base of the LCD is a p-type Si substrate (or an n-type Si substrate) made of monocrystalline silicon. At the left side of the semiconductor substrate (hereinafter referred to as p-type Si substrate) 11 in FIG. 1, a p-well region 12 is formed and is electrically isolated pixel by pixel with left and right field oxide films 13A and 13B. Within the p-well region 12, a switching element 14 is formed, which is a MOSFET (metal oxide semiconductor field effect transistor).
The switching element (hereinafter referred to as MOSFET) 14 has a gate G consisting of a gate oxide film 15 formed approximately at the center of the surface of the p-well region 12 and a gate electrode 16 made of polysilicon on the gate oxide film 15.
On the left side of the gate G of the MOSFET 14 in FIG. 1, a drain region 17 is formed, and on the drain region 17, a drain electrode 18 is formed from aluminum wiring in a first via hole Via1, to constitute a drain D.
On the right side of the gate G of the MOSFET 14 in FIG. 1, a source region 19 is formed, and on the source region 19, a source electrode 20 is formed from aluminum wiring in a first via hole Via1, to constitute a source S.
On the right side of the p-well region 12 in the p-type Si substrate 11 in FIG. 1, a diffused capacitor electrode 21 is formed by ion implantation. The diffused capacitor electrode 21 is electrically isolated pixel by pixel with the left and right field oxide films 13B and. 13C. According to the related art 1, a range from the field oxide film 13A to the field oxide film 13C corresponds to a pixel.
On the diffused capacitor electrode 21, an insulating film 22 and a capacitor electrode 23 are formed in this order. On the capacitor electrode 23, a capacitor electrode contact 24 is formed from aluminum wiring in a first via hole Via1, to constitute a storage capacitor C for the MOSFET 14.
Over the field oxide films 13A to 13C, gate electrode 16, and capacitor electrode 23, functional films including a first interlayer insulating film 25, a first metal film 26, a second interlayer insulating film 27, a second metal film 28, a third interlayer insulating film 29, and a third metal film 30 are formed one upon another in this order.
The first, second, and third interlayer insulating films 25, 27, and 29 are formed from, for example, SiO2 (silicon oxide) having an insulating ability.
The first, second, and third metal films 26, 28, and 30 are made of, for example, conductive aluminum wiring and are segmented into predetermined patterns corresponding to the pixels or the switching elements 14, respectively. Within one pixel, the first, second, and third metal films 26, 28, and 30 are electrically connected to each other. The first, second, and third metal films 26, 28, and 30 in a given pixel are electrically isolated from those in any adjacent pixel with openings 26a (FIG. 4), 28a, and 30a formed in the metal films 26, 28, and 30 between the adjacent pixels. Each of the openings 26a, 28a, and 30a has a thin width and is substantially drawn in a rectangular shape.
In each pixel, the lowermost first metal film 26 is connected to the corresponding switching element 14 and storage capacitor C.
In each pixel, the intermediate second metal film 28 serves as a light blocking metal film to block part of read light L made incident to an upper transparent substrate 33 (to be explained later) from reaching the MOSFET 14 formed under the metal film 28 on the p-type Si substrate 11. Namely, the second metal film (light blocking metal film) 28 is formed to cover the opening 30a formed between the adjacent third metal films 30 formed over the film 28 and block part of the read light L entered through the opening 30a. The second metal film 28 is connected to the lower most first metal film 26 through aluminum wiring filled in a second via hole Via2 etched in the second interlayer insulating film 27.
In each pixel, the top third metal film 30 is formed as a square reflective pixel electrode for the pixel. The metal film 30 is separated from any adjacent one by the opening 30a formed between them and is connected to the intermediate second metal film 28 through aluminum wiring filled in a third via hole Via3 etched in the third interlayer insulating film 29.
On the third metal film (hereinafter referred to as reflective pixel electrode) 30, liquid crystals 31 are sealed. On the liquid crystals 31, a transparent counter electrode 32 is formed on the reverse of the transparent substrate (glass substrate) 33, to face the reflective pixel electrodes 30. The counter electrode 32 serves as a common electrode for the reflective pixel electrodes 30, and therefore, is not segmented into pixels. The counter electrode 32 is made of for example, ITO (indium tin oxide).
In the reflective LCD 10A according to the related art 1, the active-matrix drive circuit to drive a matrix of pixels arranged in rows and columns on the p-type Si substrate 11 will be explained with reference to FIGS. 2A and 2B.
In FIGS. 2A and 2B, the active-matrix drive circuit 50 of the reflective LCD 10A according to the related art 1 drives a matrix of pixels arranged in rows and columns on the p-type Si substrate 11, each pixel composed of a MOSFET 14, a storage capacitor C connected to the MOSFET 14, and a reflective pixel electrode 30 connected to the MOSFET 14.
To select one of the pixels, a horizontal shift register circuit 51 and a vertical shift register circuit 55 are arranged in column and row directions, respectively.
For each column of pixels, the horizontal shift register circuit 51 has a video switch 52 and a signal line 53 extended from the video switch 52 in a column direction (vertical direction). For the sake of convenience of drawing, FIG. 2A shows only one signal line 53 connected to the horizontal shift register circuit 51. The signal lines 53 sequentially supply video signals. Between the horizontal shift register 51 and the video switch 52, the signal line 53 is connected to a video line 54. The signal line 53 is also connected to the drain electrodes 18 of the MOSFETs 14 that are in the same column for which the signal line 53 is provided.
For each row of pixels, the vertical shift register circuit 55 has a gate line 56 extended in a row direction (horizontal direction). For the sake of convenience of drawing, FIG. 2A shows only one gate line 56 extended from the horizontal shift register circuit 55. The gate lines 56 sequentially supply gate pulses in a scanning direction to be explained later. The gate line 56 is connected to the gate electrodes 16 of the MOSFETs 14 that are in the same row for which the gate line 56 is provided.
In each pixel, the source electrode 20 of the MOSFET 14 is connected to the capacitor electrode 23 of the storage capacitor C through the capacitor electrode contact 24 and the aluminum wiring of the first metal film 26 (FIG. 1). Also, the source electrode 20 is connected to the reflective pixel electrodes 30 through the aluminum wiring of the first and second metal films 26 and 28 (FIG. 1).
The active-matrix drive circuit 50 employs a known frame inversion driving method that inverts the polarity of video signals between positive and negative polarities frame period by frame period. For example, video signals to be written in an “n”th frame period are provided with positive polarity and those to be written in an “n+1”th frame period are provided with negative polarity. To supply a video signal through the signal line 53, the signal line 53 must be connected to one of the drain electrode 18 and source electrode 20 of the MOSFET 14. In this example, the signal line 53 is connected to the drain electrode 18 of the MOSFET 14 as mentioned above. If the signal line 53 is connected to the source electrode 20, the drain electrode 18 of the MOSFET 14 is connected to the storage capacitor C and reflective pixel electrode 30.
In the reflective LCD 10A according to the related art 1, a fixed well potential is supplied to the MOSFET 14, and a fixed common potential COM is supplied to the storage capacitor C.
The well potential to the MOSFET 14 is fixed to, for example, 15 V and is supplied between the gate line 56 and a well potential contact (not shown) on a p+ region formed in the p-well region 12 (FIG. 1). If an n-type Si substrate is employed, the well potential is, for example, 0 V.
The common potential COM to the storage capacitor C is fixed to, for example, 8.5 V and is supplied between the capacitor electrode 23 of the storage capacitor C and a common potential contact (not shown) on the diffused capacitor electrode 21. The common potential COM can basically be of any voltage to form the storage capacitor C. It may be set to a center value (for example, 8.5 V) of video signals, to make the voltage applied to the storage capacitor C about half a source voltage. Namely, a storage capacitor withstand voltage can be about half a source voltage. This enables the insulating film 22 of the storage capacitor C to be thinned to increase a capacitance value. Larger the storage capacitance value of the storage capacitor C, the smaller a potential change on the reflective pixel electrode 30. This is advantageous in preventing the flickering and burning of the liquid crystals 31 (FIG. 1).
The storage capacitor C stores charge in response to a potential difference between a potential applied to the reflective pixel electrode 30 and the common potential COM, keeps the stored voltage during an unselected period or OFF period of the MOSFET 14, and continuously applies the stored voltage to the reflective pixel electrode 30.
To drive pixels, video signals are sequentially supplied to the video lines 54 at shifted timing in the active-matrix drive circuit 50 of the reflective LCD 10A according to the related art 1. One of the video signals is supplied to the columnar signal line 53 through the video switch 52. At this time, a MOSFET 14 located at an intersection of the signal line 53 and a selected gate line 56 is selected and turned on.
The video signal is supplied to the reflective pixel electrode 30 of the selected MOSFET 14 through the signal line 53 and is written as charge into the storage capacitor C. This results in causing a potential difference between the selected reflective pixel electrode 30 and the counter electrode 32 (FIG. 1) according to the video signal and modulates the optical characteristics of the liquid crystals 31. As a result, color-image read light L (FIG. 1) emitted to the transparent substrate 33 is modulated by the liquid crystals 31 pixel by pixel, is reflected by the reflective pixel electrodes 30, and is emitted from the transparent substrate 33. Unlike the transmission LCD, the reflective LCD can utilize read light L nearly 100% to provide high-resolution, high-luminance projection images.
Parasitic capacitors will be explained with reference to FIGS. 3 to 5. On the Si substrate 11, a plurality of pixels are arranged in orthogonal columns and rows to form a matrix of pixels. In any one of the columns, parasitic capacitors are generated between pixels A and B, where the pixel A is arranged on the top side of the reflective LCD 10A relative to the pixel B in the same column and the pixel B is arranged beside and on the lower side of the pixel A in the same column.
FIG. 3 is a circuit diagram explaining the parasitic capacitors produced in the pixels A and B that are adjacent to each other in the same column in the reflective LCD according to the related art 1. FIG. 4 is a sectional view taken along the arrow line X-Y of FIG. 5, explaining the parasitic capacitors produced in the pixel A in the reflective LCD of the related art 1 where the pixels A and B are adjacent to each other in the same column. FIG. 5 is a plan view showing the semiconductor substrate (Si substrate) seen from the first metal film side along an arrow line X-Y of FIG. 4 and explaining the parasitic capacitors produced in the pixel A in the reflective LCD of the related art 1 where the pixels A and B are adjacent to each other in the same column.
In FIG. 3, the pixels A and B are arranged adjacent to each other in a columnar direction in the same column. The pixel A that is upper in the columnar direction than the pixel B involves the parasitic capacitors Ca1 and Ca2. Like the pixel A, the pixel B that is lower in the columnar direction than the pixel A involves the parasitic capacitors Cb1 and Cb2.
Between the gate line 56 of the pixel A and the source electrode 20 of the MOSFET 14 of the pixel A, the parasitic capacitor Ca1 is present. Between the source electrode 20 of the MOSFET 14 of the pixel A and the gate line 56 of the pixel B, the parasitic capacitor Ca2 is present. Like the pixel A, between the gate line 56 of the pixel B and the source electrode 20 of the MOSFET 14 of the pixel B, the parasitic capacitor Cb1 is present. Between the source electrode 20 of the MOSFET 14 of the pixel B and the gate line 56 of a pixel C, the parasitic capacitor Cb2 is present.
In FIG. 4, the source electrode 20 of the MOSFET 14 of the upper pixel A is connected to the storage capacitor C and reflective pixel electrode 30 of the pixel A. The source electrode 20 of the MOSFET 14 of the lower pixel B is connected to the storage capacitor C and reflective pixel electrode 30 of the pixel B. Under these conditions, the pixels A and B are electrically isolated from each other.
In FIG. 5 that is a plan view showing the Si substrate (semiconductor substrate) 11 seen from the first metal film 26 side along the line X-Y of FIG. 4, the areas of the pixels A and B include each the drain electrode 18, gate electrode 16, and source electrode 20 of the MOSFET 14. In each pixel area, these electrodes are arranged at an upper left part of the pixel area in a row direction (horizontal direction). At a lower part of each pixel area, the diffused capacitor electrode 21, insulating film 22 (FIG. 1), and capacitor electrode 23 are laid one upon another to form the storage capacitor C occupying a large area.
The pixel A is in one row and the pixel B is in a row that is just below the row of the pixel A. The pixels A and B receive gate pulses through the gate lines 56, respectively. Each gate line 56 is made of polysilicon and is wired in the row direction (horizontal direction) as indicated with a hatched section at an upper part of each pixel area. In the middle of each pixel area, the gate line 56 is branched in a T-shape and is connected to the gate electrode 16 of the MOSFET 14.
The pixels A and B in the same column are commonly connected to one signal line 53 that supplies a video signal to the column. The signal line 53 is made of aluminum wiring of the first metal film 26 (FIG. 4) and is laid in the columnar direction (vertical direction) as indicated with a dotted section at the left side of each pixel area. The signal line 53 is connected to the drain electrode 18 of the MOSFET 14 of each of the pixels A and B.
A connection line 57 for each of the pixels A and B is made of aluminum wiring of the first metal film 26 and is laid in the column direction (vertical direction) to drive the pixel, as indicated with a dotted section substantially at the center of each pixel area. In each of the pixels A and B, the connection line 57 is connected to the capacitor electrode contact 24 formed on the capacitor electrode 23 of the pixel and is also connected to the reflective pixel electrode 30 through aluminum wiring of the first and second metal films 26 and 28 (FIG. 4).
A common line 58 is common for the pixels A and B in the same column and supplies the common potential COM to the pixels A and B. The common line 58 is made of aluminum wiring of the first metal film 26 (FIG. 4) and is laid in the column direction (vertical direction) as indicated with a dotted section on the right side of each pixel area. The common line 58 is connected to a common potential contact 59 formed on the diffused capacitor electrode 21 of each of the pixels A and B.
A well line 60 is common for the pixels A and B in the same column and supplies a well potential to the pixels A and B. The well line 60 is made of aluminum wiring of the first metal film 26 (FIG. 4) and is laid in the column direction (vertical direction) as indicated with a dotted section on the right side of the common line 58 in each pixel area. The well line 60 is connected to a well potential contact 61 formed in the p-well region 12 (FIG. 4) of each of the pixels A and B.
With the wiring mentioned above, the parasitic capacitor Ca1 of the pixel A is produced at a part (overlap part) where the gate line 56 of the pixel A indicated with the hatched section overlaps the connection line 57 of the pixel A indicated with the dotted section. The parasitic capacitor Ca2 of the pixel A is produced at apart (overlap part) where the connection line 57 of the pixel A indicated with the dotted section overlaps the gate line 56 of the pixel B indicated with the hatched section. The sectional views of these parasitic capacitors are seen in FIG. 4. The parasitic capacitors Cb1 and Cb2 of the pixel B are not shown in FIGS. 4 and 5 but they are produced like those of the pixel A.
Actual operation in the above-mentioned structure will be considered. When the MOSFET 14 is turned off in the pixel A, a pixel potential on the reflective pixel electrode 30 of the pixel A must be retained until the MOSFET 14 is turned on in the next frame. This pixel potential retention time is, for example, 1/30 sec. During this period, a pixel potential variation must be suppressed within, for example, 5 mV. If this pixel potential variation is not kept, inconveniences such as the flickering and burning of the liquid crystals 31 (FIG. 1) occur.
In general, a parasitic capacitor produced in a pixel of an LCD changes a pixel voltage and causes flickering due to a scan line (gate line) delay. An active-matrix LCD element solving the problem of parasitic capacitors is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 2001-75127.
FIG. 6 is an equivalent circuit diagram showing an active-matrix LCD element according to a related art 2.
The active-matrix LCD element 100 of the related art 2 shown in FIG. 6 is the one disclosed in the Japanese Unexamined Patent Application Publication No. 2001-75127. With reference to the publication, the related art 2 will briefly be explained.
The active-matrix LCD element 100 of the related art 2 involves scan lines 101 arranged in a row direction (horizontal direction), signal lines 102 arranged in a column direction (vertical direction) orthogonal to the scan lines 101, and TFT elements 103 serving as switching elements formed at intersections of the lines 101 and 102.
Each scan line 101 is connected to gate electrodes G of the TFT elements 103 that are arranged in a row corresponding to the scan line 101. Each signal line 102 is connected to source electrodes S of the TFT elements 103 that are arranged in a column corresponding to the signal line 102. A drain electrode D of the TFT element 103 is connected to a liquid crystal capacitor 104, a storage capacitor 105, and a pixel electrode 107. Between the gate electrode G and drain electrode D of the TFT element 103, there is a parasitic capacitor 106. The parasitic capacitor 106 is generated due to the overlapping of the gate electrode G and drain electrode D.
In a process of forming thin film patterns for the drain electrodes D of the TFT elements 103, the related art 2 changes an exposure stage scanning speed or an exposure quantity to control a scaling correction value such that a parasitic capacitor region of an “n”th TFT element 103 becomes smaller than a parasitic capacitor region of an “n+1”th TFT element 103, the “n”th and “n+1”th TFT elements being adjacent to each other in a row direction (horizontal direction) scanned with the scan line 101. The active-matrix LCD element having such patterns involves an in-plane distribution of parasitic capacitors in connection with pixels that are adjacent to each other in the row direction, to improve the uniformity of a display screen and realize a high-quality LCD panel.
The reflective LCD 10A of the related art 1 shown in FIG. 1 is mainly used as a projector. Usage types of the projector are classified into overhead usage to suspend the projector upside down from the ceiling and desktop usage to set the projector on the floor or a shelf. The reflective LCD 10A is designed for both the usage types.
FIGS. 7A and 7B are model views showing the usage of the reflective LCD 10A of the related art 1. FIG. 7A shows the reflective LCD 10A in the overhead usage with the vertical shift register circuit 55 scanning the gate lines in a scanning direction U, and FIG. 7B shows the reflective LCD 10A in the desktop usage with the vertical shift register circuit 55 scanning the gate lines in a scanning direction D. FIGS. 8A and 8B are signal waveform diagrams of the reflective LCD 10A of the related art 1, showing the feed-through characteristics of the pixel A that differ depending on the gate line scanning directions. FIG. 8A is when the gate lines are scanned in the direction U, and FIG. 8B is when the gate lines are scanned in the direction D.
In FIG. 7A, the reflective LCD 10A of the related art 1 is in the overhead usage. A casing K is suspended from the ceiling with a bottom side Ka of the casing K facing the ceiling. The vertical shift register circuit 55 explained with reference to FIG. 2A scans the gate lines 56 in the scanning direction U row by row, thereby scanning the pixels. Namely, the pixels B and A arranged in the same column are scanned in this order from the bottom side Ka toward a top side Kb of the casing K.
In FIG. 7B, the reflective LCD 10A of the related art 1 is in the desktop usage. The bottom side Ka of the casing K is set on the floor or a shelf. In this case, the vertical shift register circuit 55 scans the gate lines 56 row by row in the scanning direction D that is opposite to the scanning direction U mentioned above, thereby scanning the pixels. Namely, the pixels A and B arranged in the same column are scanned in this order from the top side Kb toward the bottom side Ka of the casing K.
In the pixel layout of the reflective LCD 10A according to the related art 1, the different scanning directions of the gate lines 56 cause a problem that pixel voltage becomes asymmetrical from frame to frame. This is caused by the parasitic capacitors Ca1 and Ca2 of the pixel A that are formed when the pixels A and B are adjacent to each other in the same column as mentioned above.
This will be explained in more detail with reference to FIGS. 5, 8A and 8B. In FIG. 8A, the pixels A and B are arranged adjacent to each other in the same column, and the vertical shift register circuit 55 explained with reference to FIG. 2A scans the gate lines 56 in the scanning direction U to write, for example, “white” in all pixels. At this time, drive voltage waveforms generated by the frame inversion driving method will be as shown in FIG. 8A.
In this case, the pixel A that is on the top side of the reflective LCD 10A relative to the pixel B in the same column receives a video signal SIG. The video signal SIG has a signal center voltage Vsigc that is higher than a reference voltage 0 V. Around the signal center voltage Vsigc, the video signal SIG having a rectangular waveform alternates between a lower voltage Vd and a higher voltage Vp. The video signal SIG alternating between positive and negative polarities frame by frame is applied to the drain electrode 18 of the MOSFET 14 in the pixel A. Namely, in an “n”th frame (n being a natural number), the video signal SIG is set to be positive and is written into the pixel A, and in an “n+1” the frame, it is inverted to be negative and is written into the pixel A.
After the video signal SIG is applied to the pixel A in the “n”th frame, a gate pulse GAg of a voltage Vg is applied for a write time tw to the gate electrode 16 of the MOSFET 14 in the pixel A through the gate line 56 of the pixel A. This turns on the MOSFET 14 of the pixel A, to accumulate the video signal SIG as charge in the storage capacitor C of the pixel A.
At this time, the gate lines 56 are scanned in the scanning direction U, and therefore, the pixel B is driven before the pixel A. As indicated with a dotted line, a gate pulse GBg is applied to the gate electrode 16 of the MOSFET 14 in the pixel B before the gate pulse GAg is applied to the pixel A.
When the gate pulse GAg for the pixel A rises, a write signal GAs for the pixel A is applied to the reflective pixel electrode 30 of the pixel A, the write signal GAs having a pixel electrode voltage Vp whose value is substantially equal to the upper voltage Vp of the video signal SIG. At this time, the write signal GAs for the pixel A is dependent on the write characteristics, feed-through characteristics, and storage characteristics of the pixel A.
Namely, a rise of the write signal GAs for the pixel A is dependent on the write characteristics of the pixel A, which are dependent on an ON current of the MOSFET 14 of the pixel A, the write time tw, and the upper voltage Vp of the video signal SIG.
After the gate pulse GAg is applied to the gate G of the pixel A for the write time tw, the gate G is turned off. At this time, the write signal GAs for the pixel A drops below the pixel electrode voltage Vp by a feed-through voltage ?Vp1.
Thereafter, the write signal GAs for the pixel A gradually drops toward the end of the “n”th frame due to the storage characteristics of the pixel A based on the storage capacitor C connected to the reflective pixel electrode 30 of the pixel A. This storage characteristics of the pixel A are dependent on the MOSFET OFF current, storage capacitance, retention time, and leak current through liquid crystal resistance of the pixel A.
The influence of the feed-through voltage ?Vp1 in the write signal GAs for the pixel A on a pixel potential will be examined. The feed-through voltage ?Vp1 attenuates toward the reference voltage 0 V in both the positive- and negative-polarity write operations. As a result, the positive and negative display signal potentials differ from each other by the feed-through voltage ?Vp1 relative to the signal center voltage Vsigc of the video signal SIG. This results in differing the positive and negative write potentials from each other and producing a DC offset component between them. To solve this problem, a counter electrode potential Vcom must be corrected in response to the offset potential component, to balance the positive- and negative-polarity write operations.
When the gate lines 56 are scanned in the scanning direction U, the feed-through voltage ?Vp1 of the pixel A is determined by the parasitic capacitor Ca1 of the pixel A shown in FIGS. 4 and 5. The gate pulse GBg to the pixel B is applied before the gate pulse GAg to the pixel A, and therefore, the gate pulse GBg to the pixel B becomes OFF before the generation of the feed-through due to the parasitic capacitor Ca1 of the pixel A, and the potential of the gate pulse GBg to the pixel B is set (fixed) to 0 V. As a result, no feed-through is caused by the parasitic capacitor Ca2 (FIGS. 4 and 5) of the pixel A.
In FIG. 8B, the pixels A and B are arranged adjacent to each other in the same column, and the vertical shift register circuit 55 explained with reference to FIG. 2A scans the gate lines 56 in the scanning direction D, to write, for example, “white” in all pixels. At this time, drive voltage waveforms according to the frame inversion driving method will be as shown in FIG. 8B.
In an “n”th frame, a video signal SIG is applied to the pixel A. Then, a gate pulse GAg of the voltage Vg is applied for a given write time tw to the gate electrode 16 of the MOSFET 14 of the pixel A through the gate line 56 of the pixel A. Thereafter, the gate pulse GAg of the pixel A is turned off. Just after that, a gate pulse GBg of the pixel B is turned on. When the gate pulse GAg of the pixel A is turned off, a feed-through of the pixel A toward the reference voltage 0 V occurs due to the parasitic capacitor Ca1 of the pixel A shown in FIGS. 4 and 5. At this time, the gate pulse GBg of the pixel B is turned on, and therefore, the potential of the gate pulse GAg of the pixel A drops toward 0 V and the potential of the gate pulse GBg of the pixel B increases toward Vg. During the period in which the potentials of the gate pulses GAg and GBg vary, the parasitic capacitor Ca2 (FIGS. 4 and 5) of the pixel A causes a feed-through of the pixel A opposite to the reference voltage 0 V.
As a result, when the gate lines 56 are scanned in the scanning direction D, the feed-through voltage of the pixel A becomes ?Vp2, which is smaller than the feed-through voltage ?Vp1 occurring when the gate lines 56 are scanned in the scanning direction U.
This means that the counter electrode potential Vcom to cancel the DC offset component must have different values dependent upon the scanning directions U and D. If the counter electrode potential Vcom is fixed to a single value, the effect of the counter electrode potential Vcom changes when the scanning direction is changed, to generate DC components that affect the liquid crystals 31 (FIG. 4), thereby causing the flickering and burning of the liquid crystals 31.
The technical idea of the Japanese Unexamined Patent Application Publication No. 2001-75127 explained with reference to FIG. 6 may be effective to cope with parasitic capacitor regions of the “n”th and “n+1”th TFT elements 103 that are adjacent to each other in a row direction (horizontal direction). However, this related art provides no countermeasure for parasitic capacitor regions of the “m−1”th and “m”th TFT elements 103 that are adjacent to each other in a column direction (vertical direction). Accordingly, the technical idea of the Japanese Unexamined Patent Application Publication No. 2001-75127 is inapplicable to solve the feed-through problem of the related art 1 caused in the pixels A and B that are arranged adjacent to each other in a column direction (vertical direction) when changing the scanning direction of the gate lines 56 between the directions U and D.